β: This English translation is in beta — the Traditional-Chinese original is the authoritative version.
Final Exam: A 5 GHz LC VCO into a 25 Gb/s SerDes, End to End
Prerequisites: capstone_lc_end_to_end (the site-wide spine, end to end) and the three chapter exercise sets — 02 Foundations, 03 Core Theory, 06 Design Insights (finish those first) | Next: none — this is the last page. Get all 11 right and you graduate.
This is not yet another problem set. It is an exam: one design story, 11 checkpoints, from the instant a single charge impulse hits the LC tank all the way to the eye opening of a SerDes link at BER . Each question asks for exactly one "clean number", but every number requires cross-chapter dispatch — you will need [P1]'s ISF, [P2]'s κ and the App. B closed forms, the diffusion dictionary's wardrobe changes, the four clock-chain accounting rules, the PLL closed-loop algebra, and the dual-Dirac extrapolation. Work each one out yourself and type your answer first; only then expand the solution.
Design scenario (shared by the whole exam)
You own the clock path of a 25 Gb/s NRZ SerDes link (UI ps, target BER ):
| Quantity | Value | Unit | Source |
|---|---|---|---|
| VCO carrier | 5 | GHz | site-wide canonical |
| 1 | pC | Example A / Example B | |
| (representative) | 0.5 | — | Example B (a true LC gives ) |
| White-noise source | A²/Hz | Example B | |
| Measured | dBc/Hz | Example C (datasheet-grade) | |
| PLL | , type-II 2nd order | — | pll_noise_budget |
| Buffer floor | (flat) | dBc/Hz | clock_chain_budget |
| Link DJ | ps | given in Question 10 |
Two-track honesty statement (read before starting): this exam deliberately runs two sets of numbers in parallel. Ideal single-source-limit track (Questions 2, 3, 7): a single white-noise source and [P1] Eq.(21) give dBc/Hz — a physical floor no real circuit reaches. Measured track (Questions 5, 6, 9, 10): the datasheet-grade dBc/Hz — 48 dB above the ideal limit, reflecting the reality of multiple sources, cyclostationarity, flicker, and the buffer chain. The two tracks must not be mixed; each question states which track it uses.
Convention flags (exam-wide discipline): all are SSB dBc/Hz. Anything predicted from circuit noise is flagged with [P1] Eq.(21)'s SSB convention (the time-domain convention shifts the whole curve dB); anything measured ( dBc/Hz) follows the site rule and is booked with the small-angle (). The 1/f³ corner is flagged [P2] Eq.(57) vs [P1] Eq.(24) (a factor-of-2 difference). Every 2 must have a first and last name — that is itself part of what is being examined.
Act 1: Oscillator core physics (Questions 1–4)
Question 1 — One impulse into the tank (impulse → Δφ)
The story opens: the VCO is still at schematic stage. You ask the most primitive question — a charge impulse of fC sneaks in from the supply, the ISF value at the injection instant is (Example A's representative value), with pC and GHz. Find the permanent phase step and the equivalent timing error .
Question 1 — full solution (impulse → Δφ → Δt)
Step 1 (operational ISF definition, spec formula 5; derivation in impulse_to_phase_shift):
Step 2 (phase→time, spec formula 17):
Result: rad, fs (canonical Example A).
Dimension check: dimensionless C/C rad ✓; rad ÷ (rad/s) s ✓.
Story note: this 15.9 fs is a "one impulse, one-shot" displacement; the oscillator has no phase restoring force, so it stays in the phase permanently (the heart of LTV, see lti_vs_ltv). The next three questions upgrade "one impulse" to "continuous white noise".
from simulations.common.isf_utils import impulse_to_phase_step
from simulations.common.noise_utils import phase_to_time_error
dphi = impulse_to_phase_step(1e-15, 0.5, qmax=1e-12)
print(dphi, round(phase_to_time_error(dphi, 5e9)*1e15, 1)) # -> 0.0005 15.9
Question 2 — White noise paints a whole skirt (Eq.(21) → )
A single white-noise source now hits the same VCO continuously (