β: This English translation is in beta — the Traditional-Chinese original is the authoritative version.
Waveform Symmetry and Flicker Upconversion
Prerequisites: flicker_noise_upconversion (the full flicker → derivation; this page is its design-facing counterpart), fourier_series_of_isf (the ISF's Fourier coefficients and Parseval), device_noise_mapping (the of the effective ISF is the real culprit) | Next: waveform_slope, serdes_clocking_connection
This page answers a question that must be settled at the layout/topology stage: why does a waveform with symmetric rise/fall have noticeably lower close-in (near-carrier) 1/f³ phase noise? The answer is hidden entirely in one Fourier coefficient of the ISF — the DC term .
Physical intuition (conclusion first): a device's flicker noise (1/f noise, slow-varying noise in the gate/channel) is a near-DC, low-frequency noise. Low-frequency noise should not normally contaminate a high-frequency carrier — but the ISF is a periodic function, and its DC component acts like a "rectifier": it accumulates low-frequency device noise with a persistent sign into the phase, upconverting it to a close-in 1/f³ skirt near the carrier. If the rise/fall is perfectly symmetric, the ISF's positive and negative areas cancel over one period, , and this upconversion channel is shut off.
Step 1: why only upconverts flicker
Write the ISF as a Fourier series ([P1] Eq.(12), p.183):
Substitute into the LTV phase response ([P1] Eq.(13), p.183), splitting the phase into contributions from each harmonic:
- Key observation: device flicker-noise energy is concentrated near DC (). In the expression above, every term () carries a factor, which multiplies the low-frequency noise by a high-frequency carrier — a mixing operation that moves the noise to near , away from DC.
- Only the term has no carrier: it performs a pure integration of the low-frequency noise. Low-frequency noise stays nearly the same sign over an extended interval, so the integral accumulates without cancelling, continuously driving the close-in phase → upconverted into 1/f³.
- In one line: acts like a mixer (it moves the noise away), while acts like an integrator (it retains and amplifies DC noise).
Step 2: 1/f³ phase noise and the corner formula
Feed the device flicker model ([P1] Eq.(22), p.185)
into the phase noise from the -only channel to get the 1/f³ region ([P1] Eq.(23), p.185):
- Slope dimension check: (from the phase integration) times (from flicker's factor) = → dB per decade, exactly 1/f³. ✓
- Key point: the numerator is . A symmetric waveform drives → the entire 1/f³ region is suppressed.
Intersecting the 1/f³ region with the 1/f² region ([P1] Eq.(21)) defines the 1/f³ corner ([P1] Eq.(24), p.185):
Step-by-step algebra: how the corner falls out of "the two regions are equal." The corner is defined as the offset where the 1/f³ region and the 1/f² region are exactly equal in height. Setting the two (linear, not-yet-log) power spectral densities equal:
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What each step uses: the second line is just "dividing out the factors common to both sides" (pure algebra, no new physics); note that , , and are the same value in both regions, so they cancel.
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Why also cancels: the 1/f³ region is , the 1/f² region is ; dividing leaves a single — exactly the factor still on the left in line 2 above. Solving this linear equation gives the corner.
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Getting to : using Parseval ([P1] Eq.(20)) ; if the ISF is dominated by its fundamental (), then , giving .
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Dimension check: on the right, is rad/s, and is dimensionless/dimensionless = dimensionless, so is rad/s ✓.
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The most important design implication (claim C5): the 1/f³ corner is not equal to the device's 1/f corner ! It is scaled by a factor . The smaller is, the further the corner is pushed below — i.e., for the same transistor with the same device 1/f corner, simply making the waveform symmetric can push the 1/f³ skirt's knee down several decades in frequency.
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Notation trap (see notation): is the Fourier coefficient; the ISF's DC value is . Eq.(24) uses the coefficient — don't drop a factor of 2 here.
Step 3: how symmetry drives
is (twice) the ISF's average over one period:
- The ISF's shape is roughly proportional to the waveform slope (large slope near a zero crossing → large ; zero slope at the peak → ; see waveform_slope).
- If the rise and fall segments have symmetric shapes (rise slope = mirror image of fall slope), the ISF values over the rising and falling half-periods are equal in magnitude, opposite in sign, and cancel when integrated over one period → .
- An ideal LC's is exactly this kind of odd symmetry: , so an ideal LC naturally has and very weak 1/f³ upconversion.
- Asymmetry (e.g. fast rise, slow fall, or even-order harmonics that make the waveform top/bottom asymmetric) shifts the ISF's average away from 0 → .
The figure below overlays a symmetric and an asymmetric ISF: the symmetric one has its DC average pinned at 0, while the asymmetric one is lifted by a "DC offset" of — that offset is the culprit behind flicker upconversion.

Feeding actual device flicker into a simulation makes the close-in difference very clear: the asymmetric waveform shows a steep 1/f³ skirt, while the symmetric waveform shows almost none (only 1/f² and the floor remain).

Both figures are pedagogical toy models (not transistor-level): the ISF uses an analytic shape (symmetric , asymmetric , etc.), and flicker is a synthesized 1/f sequence. They faithfully illustrate " determines 1/f³" causally, but are not a measurement of any real transistor. Full scripts:
simulations/lab_05_fourier_isf.py,simulations/lab_07_flicker_noise.py.
Numerical example (building intuition)
The first example uses an assumed (illustrative); the second switches to the closed forms of [P2] Appendix B and computes and the corner directly from the topology parameters — full derivation in asymmetric_isf_closed_form.
Symmetric waveform (): theoretically , and the 1/f³ corner is pushed to extremely low frequency — in practice it is dominated by the small residual set by mismatch (see the knobs table below).
Asymmetric waveform (illustrative, assumed): take , (so ). If the device MHz, then
- Intuition: lowering from 0.4 to 0.04 (10× smaller) drops the corner by 100× () — from 320 kHz down to 3.2 kHz. In other words, each order-of-magnitude improvement in symmetry shrinks the reach of the 1/f³ skirt by two orders of magnitude — an extremely cost-effective design lever.
Asymmetric waveform (computed, directly from ring topology parameters): a ring with , , whose rise is 1.5× steeper than its fall (asymmetry ratio ). The [P2] App. B closed forms (Eq.(55)/(56)/(57), p.803; derivation in asymmetric_isf_closed_form) directly give
- Convention flag: 42.86 kHz is the [P2] Eq.(7)/(57) bookkeeping; substituting
back into [P1] Eq.(24) above yields kHz (a DC-channel weighting convention difference;
see the flag on the new page. Scalings and ratios are unaffected). The numbers are verified by
simulations/lab_33_asymmetry_corner.py(closed forms vs numeric integration, error ). - New design message ([P2]'s own sentence, p.803): at fixed the corner is — rings with fewer stages have a higher flicker corner (at : kHz, kHz). White-region phase noise is approximately N-independent ([P2] Eq.(23)), but the 1/f³ knee is pushed down by the stage count.
- Corresponding experimental evidence: [P2] Fig. 17, p.802 measures ring-oscillator phase noise vs. "symmetry control voltage," which shows a minimum at the symmetry point — direct support for the design rule "symmetric → low 1/f³." (Verified: [P2] Fig. 17, p.802, "Phase noise versus symmetry voltage for oscillator number 7" — the y-axis is the 1/f³ corner frequency, showing a clear dip to a minimum at the symmetry point.)
Design knobs for lowering (checklist)
| Knob | How | Why it lowers | Cost/notes |
|---|---|---|---|
| Symmetric rise/fall | NMOS/PMOS drive-strength or pull-up/pull-down symmetry (ring); differential topology | ISF's upper and lower half-periods cancel → average → 0 | needs sizing/bias tuning; process offset leaves residual |
| Differential / even-harmonic suppression | fully differential, symmetric loads, suppress even harmonics | even harmonics make the waveform top/bottom asymmetric → raise | 2× devices, area, power |
| Symmetric load (ring) | use a symmetric load ([P2]'s approach) instead of a single-ended inverter delay cell | matches rise/fall shape | [P2] Fig. 17's "symmetry voltage" tunes exactly this |
| Reduce DC-bias-point drift | control duty cycle near 50% | duty deviating from 50% means a DC-asymmetric waveform → | needs duty-cycle correction |
| Directly lower device flicker | use large-area, PMOS, buried-channel devices | lowers itself (does not change , but lowers the magnitude of 1/f³) | large area → large parasitic capacitance → lowers |
Note the two categories: the first four knobs change / the corner location; the last one changes the device / the overall height of 1/f³. Both can be used in design, but "making it symmetric" is usually free (no extra power) — take that shot first.
Validity and failure conditions
| Condition | Holds when | Fails when |
|---|---|---|
| Small perturbation, ISF known and fixed | fully determines 1/f³ | under large injection/strong nonlinearity the ISF itself changes |
| Device noise is pure 1/f | the model holds | with RTS/burst noise, a separate calculation is needed |
| Cyclostationarity already folded into the effective ISF | compute using |