β: This English translation is in beta — the Traditional-Chinese original is the authoritative version.
Design Chapter Exercises (with Full Solutions)
Prerequisites: tank_swing, symmetry, lc_vs_ring, pll_noise_budget, serdes_clocking_connection (every problem on this page uses the ISF formulas from these pages) | Other exercise sets: 02 Foundations chapter exercises, 03 ISF core-theory chapter exercises
This page is the complete exercise set for Chapter 06, Design Insights. The focus is on design back-calculation problems (given a target spec, solve for the knob) and comparison/trade-off problems (ring vs LC, loop-BW trade-off, tail-noise countermeasures), all answered with the ISF formulas.
Format: every solution = step-by-step substitution (with units) → result → dimension check → one-line Python verification. Python imports from
simulations/common/(includingpll_utils,serdes_utils,isf_utils,noise_utils).
Authoritative formulas involved (verified verbatim from the spec, with citations):
- The signature white-noise 1/f² result: ([P1] Eq.(21), p.185)
- 1/f³ corner: ([P1] Eq.(24), p.185)
- ring ([P2] Eq.(16), p.794; re-verified in v7: the square root covers only the constant, ; triple-checked against the body text's 4/N^1.5@η=0.75 and App. B Eq.(55). v3 had misread this as ); ring frequency ([P2] Eq.(15), p.794)
- PLL output: , see spec Section 10.2 for
- SerDes BER (RJ): , (spec Section 10.2)
- rms jitter: (spec formula 19)
Problems
Exercise 1 (design back-calculation) — , target combinations
A 5 GHz LC oscillator currently has dBc/Hz (using Eq.(21), with , pC, , which self-consistently gives when substituted into Eq.(21)). The target is to push it down another 9 dB, to dBc/Hz. List two ways to hit the target: (a) change only ; (b) change only . How much change is needed in each case?
Exercise 2 (design back-calculation) — using symmetry to suppress the corner
A ring oscillator has , , device MHz. (a) Use [P1] Eq.(24) (the exact form ) to find the corner . (b) If rise/fall symmetrization pushes down to , what does the corner become? To achieve corner < 1 kHz, what is the maximum allowed ?
Exercise 3 (comparison) — scaling for ring vs LC
(a) Using the [P2] Eq.(16) scaling , if the ring stage count is increased from to , by what factor does drop? How much does phase noise () improve, in dB? (b) In one sentence, explain why LC is usually still cleaner than ring (in terms of the two knobs and ).
Exercise 4 (design) — PLL optimal loop BW (intuition + numerical)
A ring VCO has poor intrinsic phase noise (, ), while the reference is very clean and white (, divide ratio ). Using the type-II 2nd-order transfer functions from spec Section 10.2, sweep the loop natural frequency to find the that minimizes the integrated output jitter (, integrated from 1 kHz to 100 MHz). Where would you intuitively expect to land?
Exercise 5 (numerical) — BER bathtub
A 25 Gb/s SerDes has UI ps, and the sampling clock has RJ ps (Gaussian). Find (a) the BER when sampling at the eye center (); (b) the timing margin (how far the sampling point may deviate from center) to achieve .
Exercise 6 (design back-calculation) — back-calculating the allowed from a BER budget
Same SerDes as above (UI ps); the spec requires when sampling at center. Find the maximum allowed RJ (ps). (Hint: , and .)
Exercise 7 (countermeasures) — tail-noise countermeasures (cross-coupled LC VCO)
In a cross-coupled LC VCO, tail current-source noise is upconverted by (landing near ), then folded back close-in via the ISF's component and its DC component . Using the viewpoint that "the effective ISF's are what make tail noise a problem," list three design measures for reducing the tail-noise contribution, and for each, explain why it works using one ISF quantity (, , , ). This problem is explicitly marked as illustrative.
Exercise 8 (design back-calculation) — allocating a jitter budget across PLL bands
A clock has a total rms jitter budget of fs ( GHz). The near-carrier (ref/in-band) contribution is known to be fs. RJ sources are uncorrelated (variances add). What is the maximum jitter budget (fs) left for the VCO (out-of-band)? What is the corresponding phase variance (rad²)?
Solutions in full
Exercise 1 solution (, target combinations)
Design back-calculation strategy. Inside Eq.(21), . To drop 9 dB, the linear value must drop by .
(a) Change only ():
(b) Change only ():
Result: (a) scaled up to pC; (b) pushed down to (about 1/2.82 of the original). Both give the same effect (each dB), but the cost differs: increasing requires larger swing/power, while pushing down requires improving waveform symmetry and noise-injection timing (see waveform_slope).
Consistency check: , 9 dB , ✓.
Dimension check: both ratios are dimensionless (same physical quantity divided by itself); remains in C, remains dimensionless ✓.
import numpy as np
g = 10**(9/10) # linear factor for 9 dB
print("qmax x", round(np.sqrt(g),3), "; Gamma_rms x", round(1/np.sqrt(g),3))
# -> qmax x 2.818 ; Gamma_rms x 0.355
print("new qmax", round(1.0*np.sqrt(g),2), "pC ; new Grms", round(0.7/np.sqrt(g),3))
# -> 2.82 pC ; 0.248
Exercise 2 solution (using symmetry to suppress the corner)
(a) Exact formula. [P1] Eq.(24): . Converting to (the cancels since ): .
(b) Symmetrizing to .
Upper bound on to reach corner < 1 kHz: require :
Result: (a) kHz; (b) after pushing to 0.05, kHz; to achieve corner < 1 kHz requires .
Design takeaway: the corner , so waveform symmetry (suppressing ) is the most effective knob for suppressing close-in flicker upconversion (see symmetry). arises from rise/fall asymmetry and duty-cycle deviation.
Dimension check: is dimensionless, (Hz) Hz ✓.
import numpy as np
def corner(c0, Grms=0.9, f1f=2e6): return f1f*c0**2/(2*Grms**2)
print(corner(0.3), "Hz ;", corner(0.05), "Hz") # -> 111111 ; 3086
c0_max = np.sqrt(1e3*2*0.9**2/2e6)
print("c0 <", round(c0_max,4)) # -> 0.0285
Exercise 3 solution ( scaling for ring vs LC)
(a) Scaling. [P2] Eq.(16) (re-verified in v7: the square root covers only the constant, ; triple-checked against the body text's 4/N^1.5@η=0.75 and App. B Eq.(55). v3 had misread this as ): ():
Phase noise , so the improvement is:
(b) Why LC stays cleaner. Both knobs favor LC:
- : the LC waveform is a smooth sinusoid (, , low sensitivity spread out evenly); the ring's ISF is concentrated at the transition (steep edge), giving higher rms and concentrating energy at the most sensitive point.
- : the LC tank's high permits a large voltage swing → large ; each ring stage has swing limited by and small capacitance, so is usually much smaller. Since , LC wins on both ends — smaller numerator, larger denominator.
Result: (a) drops by and improves phase noise by dB; (b) LC beats ring on both knobs — (small and spread out) and (high Q, large swing).
Note: increasing simultaneously lowers frequency () and raises power; ring's real appeal is area/tunability/no inductor, not low phase noise. See lc_vs_ring.
Dimension check: is dimensionless, is dimensionless; the ratio and the dB value are both dimensionless ✓.
import numpy as np
ratio = (15/5)**(-1.5)
print("Grms ratio", round(ratio,4), "; dPN", round(10*np.log10(ratio**2),2), "dB")
# -> Grms ratio 0.1925 ; dPN -14.31 dB
Exercise 4 solution (PLL optimal loop BW)
Intuition. The PLL low-pass filters the ref and high-pass filters the VCO (spec Section 10.2).
- If loop BW is too small → the VCO's close-in noise isn't suppressed by the loop, so in-band noise is dominated by the VCO → large jitter.
- If loop BW is too large → a large amount of ref noise (and CP noise) is let through, and the VCO high-pass corner is pushed too high, so out-of-band VCO noise is also large → large jitter.
- The optimal sits near the crossover point of the "rising ref+CP curve" and the "falling VCO curve" — where the two shaped curves intersect near , minimizing the total integrated area.
Numerical (sweeping ). Using shape_output_phase_noise and trapezoidal integration, sweep Hz,
and find the one minimizing (1 kHz→100 MHz):
Result: the optimal a few hundred kHz to ~1 MHz (near the crossover of the ref white-floor curve and the VCO curve). For this problem's parameters, the grid sweep gives Hz order of magnitude (shifts with ). This is the core trade-off in PLL noise budgeting: loop BW is neither best maximized nor minimized — an optimum exists.
Dimension check: is in rad²/Hz, is in rad² (phase variance); is in s ✓.
import numpy as np
from simulations.common.pll_utils import shape_output_phase_noise
f = np.logspace(3, 8, 4000)
S_ref = np.full_like(f, 1e-9) # white-floor reference (tuned so the optimal BW falls within the sweep range)
S_vco = 1e2 / f**2 # VCO 1/f^2
fn_grid = np.logspace(4, 7, 60)
var = []
for fn in fn_grid:
S_out, _, _ = shape_output_phase_noise(f, S_ref, S_vco, fn_hz=fn)
var.append(np.trapezoid(S_out, f)) # rad^2
fn_opt = fn_grid[int(np.argmin(var))]
print("optimal f_n ~", f"{fn_opt:.2e}", "Hz") # -> ~1.9e5 Hz (order 10^5; slightly below 10/√S_ref≈3e5 due to non-ideal brick-wall rolloff)
(See pll_noise_budget for the full plot.)
Exercise 5 solution ( BER bathtub)
(a) Center-sampled BER (). In the spec Section 10.2 RJ bathtub, at the two terms are equal:
is astronomically small () — a center-sampled error is essentially impossible.
(b) Margin for . Solve (single-sided term dominates). , so
I.e. the sampling point can deviate ps from center while still meeting ; the eye opening (@) ps (58% of UI).
Result: (a) (center is extremely safe); (b) margin ps, eye opening ps.
Dimension check: the argument of , , is dimensionless ✓; margin units are ps ✓.
import numpy as np
from scipy.special import erfcinv
from simulations.common.serdes_utils import Q, ber_bathtub
ui, sigma_t = 40e-12, 1.2e-12
print("BER(0) =", ber_bathtub(np.array([0.0]), sigma_t, ui)[0]) # ~1e-62
qinv = np.sqrt(2)*erfcinv(2*1e-12) # Q^-1(1e-12) ~ 7.03
margin = ui/2 - qinv*sigma_t
print("margin", round(margin*1e12,2), "ps ; eye", round(2*margin*1e12,1), "ps")
# -> margin 11.56 ps ; eye 23.1 ps
Exercise 6 solution (back-calculating the allowed from a BER budget)
Design back-calculation strategy. Center-sampled . Requiring means . Solving for the upper bound on :
Result: the maximum allowed RJ ps (i.e. must be , half of the common " full opening" rule: ).
Design takeaway: the tighter the BER spec ( vs ), the larger (7.94 vs 7.03), so the smaller the allowed jitter. At 25 Gb/s, requiring ps directly throws the spec back onto the clock source: use Eq.(19) to back-calculate the allowed , then back to (connect to serdes_clocking_connection).
Dimension check: ✓.
import numpy as np
from scipy.special import erfcinv
ui = 40e-12
qinv = np.sqrt(2)*erfcinv(2*1e-15) # Q^-1(1e-15) ~ 7.94
sigma_max = (ui/2)/qinv
print(round(sigma_max*1e12,3), "ps ; UI/sigma =", round(ui/sigma_max,1))
# -> 2.519 ps ; UI/sigma = 15.9
Exercise 7 solution (tail-noise countermeasures, illustrative)
Marked illustrative: the following cross-coupled LC VCO tail mechanism is a qualitative teaching model; the constants/specific depend on topology, and rigorous values require transient/adjoint extraction (see real_oscillator_topologies).
Mechanism review. The tail current source's low-frequency (including flicker) noise is upconverted by via the differential-pair switching, landing near ; it then folds back close-in via the effective ISF's (second harmonic) and its DC component , forming a / skirt. So "tail-noise trouble" is primarily written into the ISF's and .
Three countermeasures (each paired with one ISF quantity):
| Countermeasure | Why it works (ISF quantity) |
|---|---|
| Tail filter (add a notch/large capacitor at the tail) | Directly blocks tail noise near in the frequency domain → equivalently reduces the energy folded back by , suppressing close-in . |
| Waveform symmetrization (balance upper/lower half-cycles, reduce rise/fall asymmetry) | Suppresses the effective ISF's ; the corner (Eq.(24)), so directly pushes the flicker-upconversion corner away from the carrier. |
| Increase tank swing / raise | ; suppresses the contribution of every source (including the tail) together (claim C3). |
(A fourth measure as a supplement: use a device with lower noise and a lower corner for the tail, or use resistive degeneration to reduce tail noise — equivalently reducing the injected into .)
Result: tail noise is best addressed with three combined measures — "tail filter to block ," "symmetrization to suppress ," and "increase "; the corresponding quantitative knobs are (folded-back energy), (the corner ), and ().
Python verification (quantifying the effect of "symmetrization to suppress " on the corner):
import numpy as np
# Use Eq.(24) to quantify the benefit of symmetrizing to suppress c0 (f1f=2 MHz, Grms=0.9 toy values)
def f3_corner(c0, Grms=0.9, f1f=2e6): return f1f*c0**2/(2*Grms**2)
print("c0=0.3 ->", round(f3_corner(0.3)/1e3,1), "kHz ; c0=0.05 ->",
round(f3_corner(0.05)/1e3,2), "kHz")
# -> c0=0.3 -> 111.1 kHz ; c0=0.05 -> 3.09 kHz (symmetrization suppresses the corner by ~36x)
Exercise 8 solution (allocating a jitter budget across PLL bands)
Design back-calculation strategy. RJ sources are uncorrelated → variances (not rms values) add:
Step-by-step substitution (with units).
Corresponding phase variance (using , spec formula 19 reversed):
Result: VCO budget fs; corresponding rad².
Intuition: because variances add, 180 fs + 240 fs (rms) combine to 300 fs (not 420 fs) — RJ budgets must be allocated by sum of squares. This 240 fs is exactly the integrated jitter allowed for the PLL's out-of-band VCO segment, which feeds back into loop BW and VCO spec (connects to Exercise 4's optimal BW, pll_noise_budget).
Dimension check: ✓; is ✓.
import numpy as np
sigma_tot, sigma_ref, f0 = 300e-15, 180e-15, 10e9
sigma_vco = np.sqrt(sigma_tot**2 - sigma_ref**2)
sigma_phi = 2*np.pi*f0*sigma_vco
print(sigma_vco*1e15, "fs ;", sigma_phi**2, "rad^2") # -> 240.0 fs ; 2.27e-4 rad^2
Key takeaways
- / back-calculation: ; every 6 dB reduction needs or (Exercise 1).
- Symmetry: the corner ; suppressing is the most effective lever (Exercises 2, 7).
- Ring vs LC: ; LC wins on both (small/spread out) and (high Q, large swing) (Exercise 3).
- PLL optimal BW: low-pass the ref, high-pass the VCO; sits at the curve crossover, and a minimum integrated jitter exists (Exercise 4).
- BER: bathtub function; requires , requires (Exercises 5, 6).
- Tail noise: tail filter (block ) / symmetrization (suppress ) / increase , all three together (Exercise 7).
- Jitter budget: RJ sources' variances add, (Exercise 8).
- All Python verifications import from
simulations/common/(pll_utils,serdes_utils,isf_utils).
Further reading
- Increasing swing to reduce noise: tank_swing
- Waveform slope and the ISF: waveform_slope
- Symmetry suppressing : symmetry
- ring vs LC: lc_vs_ring
- PLL noise budget and optimal BW: pll_noise_budget
- Real topologies and tail noise: real_oscillator_topologies
- SerDes connection: serdes_clocking_connection
- Phase noise from tuning/supply pushing: varactor_tuning_supply_pushing
- Tank and energy restoration: tank_Q_and_energy_restoration
Other exercise sets
The same ISF machinery applied at different levels — foundational conversions, core ISF→PN derivations, complementing this page's design back-calculations:
- Foundations chapter exercises (unit conversions, PSD/jitter, random processes): 02 Foundations chapter exercises
- Core-theory chapter exercises (ISF definition, convolution, white noise→, flicker→, Fourier/Parseval): 03 ISF core-theory chapter exercises